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fix: 对齐 ?? 与静态成员复合赋值的 counter/emitter 计数,并加 projected_pc 断言
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@@ -42,21 +42,27 @@ impl Compiler {
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self.count_expression(&log.right, ctx);
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ctx.alloc_reg();
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ctx.projected_pc += 1; // AND/OR
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} else if matches!(log.operator, LogicalOperator::Coalesce) {
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// Mirror emit_logical_expression's Coalesce path: it patches raw bytecode
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// positions and does NOT consume a label id. Consuming one here would shift
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// every later construct's label id and break resolve_label at emit time.
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ctx.alloc_reg(); // dup register
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ctx.projected_pc += 1; // LOAD_VAR (DUP)
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ctx.projected_pc += 1; // JMP_IF_NULLISH
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ctx.projected_pc += 1; // JMP over RHS on non-nullish
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self.count_expression(&log.right, ctx);
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ctx.projected_pc += 1; // LOAD_VAR (overwrite)
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} else {
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let id = ctx.next_label_id();
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ctx.alloc_reg(); // dup register
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ctx.projected_pc += 1; // LOAD_VAR (DUP)
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ctx.projected_pc += 1; // JMP_IF_FALSE, JMP_IF_TRUE, or JMP_IF_NULLISH
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if matches!(log.operator, LogicalOperator::Coalesce) {
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ctx.projected_pc += 1; // JMP over RHS on non-nullish
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ctx.labels.label_map.insert(Label::TernaryElse(id), ctx.projected_pc);
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}
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ctx.projected_pc += 1; // JMP_IF_FALSE or JMP_IF_TRUE
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self.count_expression(&log.right, ctx);
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ctx.projected_pc += 1; // LOAD_VAR (overwrite)
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let skip_label = match log.operator {
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LogicalOperator::And => Label::TernaryEnd(id),
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LogicalOperator::Or => Label::TernaryElse(id),
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LogicalOperator::Coalesce => Label::TernaryEnd(id),
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LogicalOperator::Coalesce => unreachable!("coalesce handled above"),
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};
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ctx.labels.label_map.insert(skip_label, ctx.projected_pc);
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}
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